SH-2A Datasheet, PDF (388/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
Type
Category
Number Execution
of Stages States
Latency
Contention
Instructions
Single-
Floating-
5
precision point
floating- register-
point
register
instructions transfer
instructions
1
0 • These instruc- FLDS FRm,FPUL
tions use the
FPU load/store
FMOV
FRm,FRn
pipeline.
FSTS FPUL,FRn
Floating-
5
point
register-
immediate
instructions
1
0 • These instruc- FLDI0 FRn
tions use the
FPU load/store
FLDI1
FRn
pipeline.
FSCHG
5
instruction
Floating-
5
point
register
load
instructions
4
1
1 • This instruction FSCHG
uses the FPU
arithmetic
operation
pipeline.
1
0/2^*3 • These instruc- FMOV.S @Rm,FRn
1
1/2^*3
tions use the
FPU load/store
FMOV.S
@Rm+,FRn
0/2^*3 _{pipeline and}
FMOV.S @(R0,Rm),FRn
memory access
pipeline.
1
0/2^*3 • This is 32-bit FMOV.S @(disp12,Rm),FRn
instruction.
• This instruction
uses the FPU
load/store
pipeline and
memory access
pipeline.
Floating-
4
point
register
store
instructions
1
0 • These instruc- FMOV.S FRm,@Rn
1/0^*3
tions use the
FPU load/store
FMOV.S
FRm,@-Rn
0
pipeline and
FMOV.S FRm,@ (R0,Rn)
memory access
pipeline.
• This is 32-bit
instruction.
FMOV.S FRm,@(disp12,Rn)
• This instruction
uses the FPU
load/store
pipeline and
memory access
pipeline.
Rev. 3.00 Jul 08, 2005 page 374 of 484
REJ09B0051-0300