SH-2A Datasheet, PDF (23/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 2 Programming Model
QIS: sNaN is treated as qNaN or ±∞. Valid only when the V bit in the enable field of FPSCR is
set to 1.
• QIS = 0: Processed as qNaN or ±∞.
• QIS = 1: Exception generated (processed same as sNaN).
SZ: Transfer Size Mode
• SZ = 0: The data size of an FMOV instruction is 32 bits.
• SZ = 1: The data size of an FMOV instruction is a 32-bit pair (64 bits).
PR: Precision Mode
• PR = 0: Floating-point instructions are executed as single-precision operations.
• PR = 1: Floating-point instructions are executed as double-precision operations (the result of
an instruction for which double-precision is not supported is undefined).
DN: Denormalization Mode (always 1)
• DN = 1: A denormalized number is treated as zero.
Cause: FPU exception cause field
Enable: FPU exception enable field
Flag: FPU exception flag field
FPU Error
(E)
Invalid
Operation
(V)
Division
by Zero
(Z)
Overflow
(O)
Underflow
(U)
Inexact
Exception
(I)
Cause FPU exception Bit 17
cause field
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Enable FPU exception None
enable field
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Flag FPU exception None
flag field
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
When an FPU operation instruction is executed, the FPU exception cause field is initially set to 0.
When an FPU exception next occurs, the corresponding bit in the FPU exception cause field and
FPU exception flag field is set to 1.
The FPU exception flag field retains the status of an exception generated after that field was last
cleared.
Rev. 3.00 Jul 08, 2005 page 9 of 484
REJ09B0051-0300