SH-2A Datasheet, PDF (53/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 4 Instruction Features
Addressing Instruction
Mode
Format
Indirect
indexed
GBR
addressing
@(R0,
GBR)
Effective Addresses Calculation
The effective address is the GBR value plus R0.
GBR
+
GBR + R0
Formula
GBR + R0
R0
TBR
@@(disp:8,
duplicate TBR)
indirect with
displacement
Effective address is register TBR contents with 8-bit
displacement disp added. After disp is zero-
extended, it is multiplied by 4.
(TBR + disp x
4) address
contents
TBR
disp
(zero-extended)
+
TBR
+ disp 4
PC relative
addressing
with
displace-
ment
@(disp:8,
PC)
(TBR
4
+ disp 4)
The effective address is the PC value plus an 8-bit
displacement (disp). The value of disp is zero-
extended, and disp is doubled for a word operation,
or is quadrupled for a longword operation. For a
longword operation, the lowest two bits of the PC are
masked.
Word: PC +
disp × 2
Longword:
PC &
H'FFFFFFFC
+ disp × 4
PC
H'FFFFFFFC
disp
(zero-extended)
(for longword)
&
PC + disp 2
or
+ _{PC&H'FFFFFFFC}
+ disp 4
x
2/4
Rev. 3.00 Jul 08, 2005 page 39 of 484
REJ09B0051-0300