SH-2A Datasheet, PDF (242/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.4.34
MOVA
Effective Address
Transfer
MOVe effective Address
Data Transfer Instruction
Format
MOVA @(disp,PC),R0
Abstract
disp × 4 + PC → R0
Code
Cycle T Bit
11000111dddddddd 1
—
Description
Stores the effective address of the source operand into general register R0. The 8-bit displacement
is zero-extended and quadrupled. Consequently, the relative interval from the operand is PC +
1020 bytes. The PC is the address four bytes after this instruction, but the lowest two bits of the
PC are corrected to B'00.
Note
If this instruction is placed immediately after a delayed branch instruction, the PC must point to an
address specified by (the starting address of the branch destination) + 2.
For the Renesas Technology Super H RISC engine assembler, declarations should use scaled
values (×4) as displacement values.
Operation
MOVA(long d) /* MOVA @(disp,PC),R0 */
{
long disp;
disp=(0x000000FF & (long)d);
R[0]=(PC&0xFFFFFFFC)+(disp<<2);
PC+=2;
}
Rev. 3.00 Jul 08, 2005 page 228 of 484
REJ09B0051-0300