SH-2A Datasheet, PDF (161/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.3.31 RTS/N ReTurn from Subroutine with No delay slot Branch Instruction
Return from Subroutine Procedure with No Delay Slot
SH-2A/SH2A-FPU (New)
Format
RTS/N
Abstract
PR → PC
Code
0000000001101011
Cycle
3
T Bit
―
Description
Performs a return from a subroutine procedure. That is, the PC is restored from PR, and
processing is resumed from the address indicated by the PC. This instruction enables a return to
be made from a subroutine procedure called by a BSR or JSR instruction to the origin of the call.
Note
This is not a delayed branch instruction.
Operation
RTSN ( ) /* RTS/N */
{
PC=PR+4;
}
Examples:
TABLE:
TRGET:
MOV.L TABLE,R3
JSR/N @R3
ADD R0,R1
........
.data.1 TRGET
........
NOP
MOV R2,R3
RTS/N
; R0 = TRGET address
; Branch to TRGET.
; ← Procedure return destination
(PR contents)
; Jump table
; ← Entry to procedure
;
; Return to above ADD instruction.
Rev. 3.00 Jul 08, 2005 page 147 of 484
REJ09B0051-0300