SH-2A Datasheet, PDF (137/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.3.18 LDC
LoaD to Control register
Load to Control Register
Section 6 Instruction Descriptions
System Control Instruction
SH-2A/SH2A-FPU (New)
Format
LDC Rm, TBR
Abstract
Rm → TBR
Code
0100mmmm01001010
Cycle
1
T Bit
―
Description
Stores a source operand in control register TBR.
Operation
LDCTBR (long m)
{
TBR=R[m];
PC+=2;
}
/* LDC Rm, TBR*/
Examples:
LDC R0,TBR
; Before execution: R0 = H'12345678, TBR = H'00000000
; After execution: TBR = H'12345678
Rev. 3.00 Jul 08, 2005 page 123 of 484
REJ09B0051-0300