SH-2A Datasheet, PDF (324/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.5.14
FNEG
Floating-Point
Sign Inversion
Floating-point NEGate value
Floating-Point Instruction
PR Format
0
FNEG FRn
1
FNEG DRn
Abstract
-FRn → FRn
-DRn → DRn
Code
Cycle
1111nnnn01001101 1
1111nnn001001101 1
T Bit
—
—
Description
This instruction inverts the most significant bit (sign bit) of the contents of floating-point register
FRn/DRn, and stores the result in FRn/DRn.
The cause and flag fields in FPSCR are not updated.
Operation
void FNEG (int n){
FR[n] = -FR[n];
pc += 2;
}
/* Same operation is performed regardless of precision. */
Possible Exceptions:
None
Rev. 3.00 Jul 08, 2005 page 310 of 484
REJ09B0051-0300