SH-2A Datasheet, PDF (351/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
• SF: FPU store
The floating-point operation is completed, and the result is written to an FPU register.
• ED: FPU division and square root calculation
Used only for FDIV and FSQRT.
• EX: FPU load/store stage 1
Floating-point load/store instruction data preparation is performed.
• NA: FPU load/store stage 2
Floating-point load/store instruction data exchange is performed.
The length of all stages after ID and DF is the same. Only IF may be extended due to a wait for
data, but as the instruction fetch unit and pipelines operate independently, pipelining can be
continued in this case, also, for instructions that have already been fetched.
As shown in figure 8.2, instruction stages continue to flow together with instruction execution,
forming a pipeline. The basic pipeline flow is shown in figure 8.1. The interval during which one
stage is executed is called a slot, and is indicated by “↔”. Each instruction has at least a 3-stage
structure.
The three stages IF, ID, and EX (integer pipeline) are present for each instruction. Thereafter,
instruction processing is performed with the necessary pipelines operating simultaneously.
Rev. 3.00 Jul 08, 2005 page 337 of 484
REJ09B0051-0300