SH-2A Datasheet, PDF (217/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.4.26
LDC
Load to Control
Register
LoaD to Control register
Section 6 Instruction Descriptions
System Control Instruction
Format
LDC Rm,SR
LDC Rm,GBR
LDC Rm,VBR
LDC.L @Rm+,SR
LDC.L @Rm+,GBR
LDC.L @Rm+,VBR
Abstract
Rm → SR
Rm → GBR
Rm → VBR
(Rm) → SR, Rm + 4 → Rm
(Rm) → GBR, Rm + 4 → Rm
(Rm) → VBR, Rm + 4 → Rm
Code
Cycle T Bit
0100mmmm00001110 3
LSB
0100mmmm00011110 1
—
0100mmmm00101110 1
—
0100mmmm00000111 5
LSB
0100mmmm00010111 1
—
0100mmmm00100111 1
—
Description
Store the source operand into control register SR, GBR, or VBR.
Operation
LDCSR(long m) /* LDC Rm,SR */
{
SR=R[m]&0x000063F3;
PC+=2;
}
LDCGBR(long m) /* LDC Rm,GBR */
{
GBR=R[m];
PC+=2;
}
LDCVBR(long m) /* LDC Rm,VBR */
{
VBR=R[m];
PC+=2;
}
LDCMSR(long m) /* LDC.L @Rm+,SR */
{
SR=Read_Long(R[m])&0x000063F3;
Rev. 3.00 Jul 08, 2005 page 203 of 484
REJ09B0051-0300