SH-2A Datasheet, PDF (425/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

(7) Memory Bit Operation Instructions
Section 8 Pipeline Operation
Instruction Types
BCLR.B #imm3,@(disp12,Rn)
BSET.B #imm3,@(disp12,Rn)
BST.B #imm3,@(disp12,Rn)
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA EX MA
IF — — ID EX ⋅ ⋅ ⋅
IF — — — ID EX ⋅ ⋅ ⋅
Operation
The pipeline ends after six stages: IF, ID, EX, MA, EX, MA.
Instruction Issuance
These instructions use the memory access pipeline.
Parallel Execution Capability
These are 32-bit instructions, and cannot be used in parallel execution. (See section 8.3.5, Details
of Contention Due to 32-Bit Instruction.)
Rev. 3.00 Jul 08, 2005 page 411 of 484
REJ09B0051-0300