SH-2A Datasheet, PDF (456/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(17) SLEEP Instruction
Instruction Type
SLEEP
Pipeline
SLEEP
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX ⋅ ⋅ ⋅ EX EX
IF — ⋅ ⋅ ⋅
IF — ⋅ ⋅ ⋅
Operation
The pipeline ends after seven stages: IF, ID, EX, MA, EX, EX, EX.
After a SLEEP instruction is executed, sleep mode or standby mode is entered.
Instruction Issuance
This instruction uses the memory access pipeline.
Parallel Execution Capability
This is a multi-cycle instruction, and cannot be executed in parallel with a subsequent instruction.
Rev. 3.00 Jul 08, 2005 page 442 of 484
REJ09B0051-0300