SH-2A Datasheet, PDF (490/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
2. Counting Execution State Cycles
MOV.L
ADD
MOV.L
@ R1, R0
# imm, R2
R3, @ R4
↔
↔
ID
ID
↔
EX
EX
ID
↔
MA
EX
↔
WB
MA
↔
↔
↔
Cycles
1→0
1
In this case, the result from the previously issued instruction is not used by the instructions that
follow it, so the instructions execute in parallel provided no resource contention occurs. The
number of cycles required by each instruction to execute are calculated in the “execution state.”
When the preceding instruction uses one execution state cycle, the following instruction executes
in parallel. When parallel execution takes place, the number of cycles required by the preceding
instruction is calculated as “execution state” minus one. This serves as a simplified compensation.
(This compensation appears as the final item in the equation introduced below.)
3. If Resource Contention Occurs
MOV.L
MOV.L
MOV.L
@ R1, R0
@ R3, R2
@ R5, R4
↔
↔
ID
↔
EX
ID
↔
MA
EX
ID
↔
WB
MA
EX
↔
WB
MA
↔
WB
↔
Cycles
1
1
If resource contention occurs, parallel execution is not possible. The execution of each instruction
requires “execution state” cycles.
4. Instructions Using More Than One Execution State
↔
AND.B # imm, @(R0,GBR)
ADD # imm, R1
BAND.B # imm, @(disp12,R2)
ROTCL
↔
ID
↔
EX
↔
MA
ID
↔
EX
EX
ID
↔
EX
↔
MA
↔
EX
ID
Cycles
3→2
1
3
For instructions using more than one execution state, the calculation assumes that the number of
remaining states is reduced one by one until only one remains, at which point parallel execution
with the subsequent instructions is possible. In this case, the number of cycles required for
execution is calculated as “execution state” minus one if parallel execution with subsequent
instructions takes place, and as “execution state” if no parallel execution takes place. This serves
Rev. 3.00 Jul 08, 2005 page 476 of 484
REJ09B0051-0300