SH-2A Datasheet, PDF (44/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 3 Exception Handling
FADD, FSUB, FMUL, FDIV, FMAC, FCMP/EQ, FCMP/GT, FLOAT, FTRC,
FCNVDS, FCNVSD, FSQRT
An FPU exception is generated only when the corresponding enable bit is set. When the FPU
detects an exception, FPU operation is halted and exception generation is reported to the CPU.
When exception handling is started, CPU operations are as follows.
1. The start address of the exception service routine stored in VBR + H'00000034 is fetched from
the exception handling vector table.
2. SR contents are saved on the stack.
3. PC is saved on the stack. The PC value saved is the start address of the instruction following
the last instruction executed.
4. Control branches to the address stored in VBR + H'00000034.
The exception flag bits in FPSCR are always updated regardless of whether or not an FPU
exception has been accepted, and remain set until explicitly cleared by the user by means of an
instruction. The FPSCR source bits change each time an FPU instruction is executed.
When the V bit in the enable field of the FPSCR register is set and the QIS bit in FPSCR is also
set, FPU exception handling is started when qNaN or ±∞ is input to a floating-point operation
instruction source.
3.8 Cases in Which Exceptions Are Not Accepted
There are cases, as shown in table 3.9, in which, if an address error, RAM error, FPU exception,
register bank error (overflow), or interrupt occurs immediately after a delayed branch instruction,
the exception is not accepted immediately, but is held pending. In such cases, the exception will
be accepted when an instruction for which exception acceptance is permitted is decoded.
Table 3.9 Exception Source Occurrence Immediately after Delayed Branch Instruction
Exception Source
Address
Point of Occurrence Error
FPU
Register Bank
RAM Error Exception Error (Overflow) Interrupt
Immediately after a ×
×
×
×
×
delayed branch
instruction*
Notes: ×: Not accepted
* Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Rev. 3.00 Jul 08, 2005 page 30 of 484
REJ09B0051-0300