SH-2A Datasheet, PDF (40/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 3 Exception Handling
Table 3.7 Interrupt Priority Levels
Type
NMI
User break
H-UDI
External interrupt (IRQ),
on-chip peripheral module
Priority Level
16
15
15
0 to 15
Notes
Fixed priority level, not maskable
Fixed priority level
Fixed priority level
Can be set in interrupt priority level setting
register
3.6.3 Interrupt Exception Handling
When an interrupt occurs, its priority is determined by the interrupt controller (INTC). NMI is
always accepted, but other interrupts are only accepted if their priority level is higher than the
priority level set in the interrupt mask bits (I3 to I0) in the status register (SR).
When an interrupt is accepted, interrupt exception handling is started. In interrupt exception
handling, the CPU saves SR and the program counter (PC) on the stack. In interrupt exception
handling other than NMI, UBC, when register bank use has been set, general registers R0 to R14,
control register GBR, system registers MACH, MACL, and PR, and the vector table address offset
of the interrupt exception handling to be executed, are saved to the register bank. In the case of
exception handling due to an address error, RAM error, register bank error, NMI interrupt, UBC
interrupt, or instruction, saving to a register bank is not performed. Also, when saving is
performed to all register banks, automatic saving to the stack is performed instead of register bank
saving. In this case, an interrupt controller setting must have been made for register bank
overflow exceptions not to be accepted. If a setting has been made for register bank overflow
exceptions to be accepted, a register bank overflow exception will be generated. The interrupt
priority level of the accepted interrupt is then written to bits I3 to I0 in SR. In the case of NMI,
however, although its priority level is 16, H'F (level 15) is written to bits I3 to I0. Next, the CPU
fetches the exception service routine start address from the exception vector table entry
corresponding to the accepted interrupt, jumps to that address, and starts executing the exception
service routine. For details of interrupt exception handling, see “Operation” in the Interrupt
Controller section of the hardware manual for the relevant product.
Rev. 3.00 Jul 08, 2005 page 26 of 484
REJ09B0051-0300