SH-2A Datasheet, PDF (445/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

(9) Memory → MAC Transfer Instructions
Instruction Types
LDS.L @Rm+,MACH
LDS.L @Rm+,MACL
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA WB
IF ID EX ⋅ ⋅ ⋅
IF ID EX ⋅ ⋅ ⋅
Section 8 Pipeline Operation
Operation
The pipeline ends after five stages: IF, ID, EX, MA, WB.
See section 8.7, Contention Due to Multiplier, for general pipeline details. This instruction has
one execution slot, a latency of three, and two lock states. Detailed examples where there are
consecutive instructions relating to the pipeline of this instruction or the multiplier are given
below.
(a) When an LDS.L instruction is immediately followed by a MAC.W or MAC.L instruction
There is no multiplier contention, but there is memory access contention, with 1-cycle stalling.
LDS.L @Rm+,MACH
MAC.W @Rm+,@Rn+
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA WB
IF — ID EX MA MA mm mm
IF — — ID EX ⋅ ⋅ ⋅
Rev. 3.00 Jul 08, 2005 page 431 of 484
REJ09B0051-0300