SH-2A Datasheet, PDF (283/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.4.65
TRAPA
Trap Exception
Handling
TRAP Always
Section 6 Instruction Descriptions
System Control Instruction
Format
TRAPA #imm
Abstract
PC/SR → Stack area, (imm × 4 + VBR)
→ PC
Code
Cycle
11000011iiiiiiii 5
T Bit
—
Description
Starts the trap exception processing. The PC and SR values are stored on the stack, and the
program branches to an address specified by the vector. The vector is a memory address obtained
by zero-extending the 8-bit immediate data and then quadrupling it. The PC is the start address of
the next instruction. TRAPA and RTE are both used together for system calls.
Note
For the Renesas Technology Super H RISC engine assembler, declarations should use scaled
values (×4) as displacement values.
Operation
TRAPA(long i) /* TRAPA #imm */
{
long imm;
imm=(0x000000FF & i);
R[15]-=4;
Write_Long(R[15],SR);
R[15]-=4;
Write_Long(R[15],PC–2);
PC=Read_Long(VBR+(imm<<2))+4;
}
Rev. 3.00 Jul 08, 2005 page 269 of 484
REJ09B0051-0300