 English |
|
|
|
|
|
|
|
| SH-2A Datasheet, PDF (284/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family | |||
| |||
| ◁ |
Section 6 Instruction Descriptions
Example:
Address
VBR+H'80 .data.l 10000000 ;
..........
TRAPA
TST
#H'20
#0,R0
; Branches to an address specified by data in address VBR + H'80
; â Return address from the trap routine (stacked PC value)
...........
..........
100000000 XOR
100000002 RTE
100000004 NOP
R0,R0
; â Trap routine entrance
; Returns to the TST instruction
; Executes NOP before RTE
Rev. 3.00 Jul 08, 2005 page 270 of 484
REJ09B0051-0300
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese