SH-2A Datasheet, PDF (30/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 3 Exception Handling
Table 3.1 Exception Types and Priority
Exception Handling
Priority
Reset
Power-on reset
High
Manual reset
Address errors CPU address error
DMAC address error
RAM errors
RAM error
Instructions
FPU exception
Integer division exception (division by zero)
Integer division exception (overflow)
Register bank
errors
Bank underflow
Bank overflow
Interrupts
NMI
User break
H-UDI
External interrupt (IRQ)
On-chip peripheral modules
Instructions
Trap instruction (TRAPA instruction)
General illegal instruction (undefined code)
Slot illegal instruction (undefined code (FPU instruction or FPU-
related CPU instruction in module standby status including FPU or in
product with no FPU, or register bank-related instruction^*2 in product
with no register bank) located immediately after delayed branch
instruction^*1, instruction that modifies PC^*3, 32-bit instruction^*4,
RESBANK instruction, DIVS instruction, or DIVU instruction)
Low
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
2. Register bank-related instructions: RESBANK, LDBANK, STBANK
3. Instructions that modify PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S,
BT/S, BSRF, BRAF, JSR/N, RTV/N
4. 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B,
BORNOT.B, BSET.B, BST.B, BXOR.B, FMOV.S @disp12, FMOV.D @disp12,
MOV.B @disp12, MOV.W @disp12, MOV.L @disp12, MOVI20, MOVI20S, MOVU.B,
MOVU.W
Rev. 3.00 Jul 08, 2005 page 16 of 484
REJ09B0051-0300