SH-2A Datasheet, PDF (205/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Example 3:
SHLL16
EXTS.W
XOR
MOV
ROTCL
SUBC
DIV0S
.arepeat
DIV1
.aendr
EXTS.W
ROTCL
ADDC
EXTS.W
R0
R1,R1
R2,R2
R1,R3
R3
R2,R1
R0,R1
16
R0,R1
R1,R1
R1
R2,R1
R1,R1
Section 6 Instruction Descriptions
; R1 (16 bits)/R0 (16 bits) = R1 (16 bits):Signed
; Upper 16 bits = divisor, lower 16 bits = 0
; Sign-extends the dividend to 32 bits
; R2 = 0
;
;
; Decrements if the dividend is negative
; Flag initialization
;
; Repeat 16 times
;
; R1 = quotient (one’s complement)
; Increments and takes the two’s complement if the MSB of the quotient is 1
; R1 = quotient (two’s complement)
Example 4:
MOV
ROTCL
SUBC
XOR
SUBC
DIV0S
.arepeat
ROTCL
DIV1
.aendr
ROTCL
ADDC
R2,R3
R3
R1,R1
R3,R3
R3,R2
R0,R1
32
R2
R0,R1
R2
R3,R2
; R2 (32 bits) / R0 (32 bits) = R2 (32 bits):Signed
;
;
; Sign-extends the dividend to 64 bits (R1:R2)
; R3 = 0
; Decrements and takes the one’s complement if the dividend is negative
; Flag initialization
;
; Repeat 32 times
;
;
; R2 = Quotient (one’s complement)
; Increments and takes the two’s complement if the MSB of the quotient is 1.
R2 = Quotient (two’s complement)
Rev. 3.00 Jul 08, 2005 page 191 of 484
REJ09B0051-0300