SH-2A Datasheet, PDF (201/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.4.18 DIV1
Division
DIVide 1 step
Section 6 Instruction Descriptions
Arithmetic Instruction
Format
DIV1 Rm,Rn
Abstract
1 step division (Rn ÷ Rm)
Code
Cycle T Bit
0011nnnnmmmm0100 1
Calculation result
Description
Uses single-step division to divide one bit of the 32-bit data in general register Rn (dividend) by
Rm data (divisor). It finds a quotient through repetition either independently or used in
combination with other instructions. During this repetition, do not rewrite the specified register or
the M, Q, and T bits.
In one-step division, the dividend is shifted one bit left, the divisor is subtracted and the quotient
bit reflected in the Q bit according to the status (positive or negative). To find the remainder in a
division, first find the quotient using a DIV1 instruction, then find the remainder as follows:
(dividend) – (divisor) × (quotient) = (remainder)
Zero division, overflow detection, and remainder operation are not supported. Check for zero
division and overflow division before dividing.
Find the remainder by first finding the sum of the divisor and the quotient obtained and then
subtracting it from the dividend. That is, first initialize with DIV0S or DIV0U. Repeat DIV1 for
each bit of the divisor to obtain the quotient. When the quotient requires 17 or more bits, place
ROTCL before DIV1. For the division sequence, see the following examples.
Rev. 3.00 Jul 08, 2005 page 187 of 484
REJ09B0051-0300