SH-2A Datasheet, PDF (127/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.3.13 DIVS
Signed Division
DIVide as Signed
Format
DIVS R0,Rn
Abstract
Signed, Rn ÷ R0 → Rn
Section 6 Instruction Descriptions
Arithmetic Instruction
SH-2A/SH2A-FPU (New)
Code
0100nnnn10010100
Cycle
36
T Bit
―
Description
Executes division of the 32-bit contents of a general register Rn (dividend) by the contents of R0
(divisor). This instruction executes signed division and finds the quotient only. A remainder
operation is not provided. To obtain the remainder, find the product of the divisor and the
obtained quotient, and subtract this value from the dividend. The sign of the remainder will be the
same as that of the dividend.
Notes
An overflow exception will occur if the negative maximum value (H'00000000) is divided by –1.
If division by zero is performed a division by zero exception will occur.
If an interrupt is generated while this instruction is being executed, execution will be halted. The
return address will be the start address of this instruction, and this instruction will be re-executed.
Operation
DIVS (long n) /* DIVS
{
R[n]=R[n] / R[0];
PC+=2;
}
R0, Rn */
Examples:
DIVS R0,R1
; R1(32bits) / R0 (32bits) = R1(32bits); signed
Rev. 3.00 Jul 08, 2005 page 113 of 484
REJ09B0051-0300