SH-2A Datasheet, PDF (491/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
as a simplified compensation. (This compensation appears as the final item in the equation
introduced below.)
Based on the above, the number of cycles necessary to execute the entire instruction string is as
summarized below, in extremely simplified terms. If some portions of the string have
dependencies and others do not, separate calculations should be made for each portion and the
results added together.
• If Dependencies Exist Between Instructions
Required number of cycles = sum total of “latency” cycles of all instructions
• If No Dependencies Exist Between Instructions
Required number of cycles = sum total of “execution state” cycles of all instructions– (total
number of instructions – number of instructions that cannon be executed in parallel) ÷ 2
In this case, “number of instructions that cannon be executed in parallel” is the total number of
instructions that cannot be executed in parallel due to resource contention (in particular, memory
access instructions that immediately follow another memory access instruction), instructions using
more than one execution state, and 32-bit instructions
The final item compensates for the effects of parallel execution by reducing the number of
required cycles for the preceding instructions.
Example: If Dependencies Exist Between Instructions
BAND.B
ROTCL
BAND.B
ROTCL
The “latency” cycles for all instructions are added together, producing a total of eight cycles.
Example: If No Dependencies Exist Between Instructions
ADD
BAND.B
MULR
ROTCL
# imm, R0
# imm, @(disp12,R2)
R4, R0
R5
Required number of cycles = 1 + 3 + 2 + 1 – (4 – 2) ÷ 2
= 7 – 1 = 6 cycles
Rev. 3.00 Jul 08, 2005 page 477 of 484
REJ09B0051-0300