SH-2A Datasheet, PDF (65/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 5 Instruction Set
Classification
Floating-point
instructions
Instruction
Type
Op Code
19
FABS
FADD
FCMP
FCNVDS
FCNVSD
FDIV
FLDI0
FLDI1
FLDS
FLOAT
FMAC
FMOV
FMUL
FNEG
FSCHG
FSQRT
FSTS
FSUB
FTRC
FPU-related
2
LDS
CPU instructions
STS
Function
Number of
Instructions
Floating-point absolute value
48
Floating-point addition
Floating-point comparison
Conversion from double-precision to
single-precision
Conversion from single-precision to
double-precision
Floating-point division
Floating-point load immediate 0
Floating-point load immediate 1
Floating-point load into system register
FPUL
Conversion from integer to floating-
point
Floating-point multiply and accumulate
operation
Floating-point data transfer
Floating-point multiplication
Floating-point sign inversion
SZ bit inversion
Floating-point square root
Floating-point store from system
register FPUL
Floating-point subtraction
Floating-point conversion with
rounding to integer
Load into floating-point system register 8
Store from floating-point system
register
Rev. 3.00 Jul 08, 2005 page 51 of 484
REJ09B0051-0300