SH-2A Datasheet, PDF (461/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(4) FPU Exception Handling
Instruction Type
FPU exception handling
Pipeline
FPU exception
handling
Next instruction
Instruction after next
Branch destination
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX EX MA MA MA
IF ⋅ ⋅ ⋅
IF ⋅ ⋅ ⋅
IF ID
Operation
An FPU execution is accepted in the ID stage of an instruction, and processing from that ID stage
onward is replaced by the FPU exception handling sequence.
The pipeline ends after six stages: IF, ID, EX, MA, MA, MA. FPU exception handling is not a
delayed branch. The IF stage of the branch destination instruction is started from the slot
containing the last MA stage of the FPU exception handling.
Pipeline Processing of Instructions from Generation to Acceptance of FPU Exceptions
The FPU makes the instruction at which the execution occurred an NOP instruction, and also
makes FPU instructions (excluding FCMP instructions) from occurrence of the execution to the
instruction that accepts the exception NOP instructions. Consequently, FPU registers are not
updated by instructions during this interval.
With FPU-related CPU instructions, as above, FPU registers are not updated (NOP operation is
performed), but CPU registers are updated.
CPU instructions are not made NOP instructions, and operate as usual.
Rev. 3.00 Jul 08, 2005 page 447 of 484
REJ09B0051-0300