SH-2A Datasheet, PDF (50/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 4 Instruction Features
(11) Absolute Address
When data is accessed by absolute address, the value already in the absolute address is placed in
the memory table. Loading the immediate data when the instruction is executed transfers that
value to the register and the data is accessed in the indirect register addressing mode.
With the SH-2A/SH2A-FPU, when data is referenced using an absolute address not exceeding 28
bits, it is also possible to transfer immediate data located in the instruction code to a register, and
reference the data using register indirect addressing mode. However, when referencing data using
an absolute address of 21 to 28 bits, an OR instruction must be used after the register transfer.
Table 4.5 Referencing by Means of Absolute Address
Type
Up to 20 bits
21 to 28 bits
29 bits or more
SH-2A/SH2A-FPU CPU
MOVI20 #H'12345, R1
MOV.B @R1, R0
MOVI20S #H'12345, R1
OR
#H'67, R1
MOV.B @R1, R0
MOV.L @(disp,PC),R1
MOV.B @R1,R0
..........
.DATA.L H'12345678
Example for Other CPU
MOV.B @H'12345,R0
MOV.B @H'1234567,R0
MOV.B @H'12345678,R0
(12) 16-Bit/32-Bit Displacement
When data is accessed by 16-bit or 32-bit displacement, the pre-existing displacement value is
placed in the memory table. Loading the immediate data when the instruction is executed transfers
that value to the register and the data is accessed in the indirect indexed register addressing mode.
Table 4.6 Displacement Accessing
Type
16-bit displacement
SH-2A/SH2A-FPU CPU
MOV.W @(disp,PC),R0
MOV.W @(R0,R1),R2
..................
.DATA.W H'1234
Example for Other CPU
MOV.W @(H'1234,R1),R2
Rev. 3.00 Jul 08, 2005 page 36 of 484
REJ09B0051-0300