SH-2A Datasheet, PDF (401/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

(8) Memory Store Instructions (12-Bit Displacement)
Instruction Types
MOV.B
MOV.W
MOV.L
Rm,@(disp12,Rn)
Rm,@(disp12,Rn)
Rm,@(disp12,Rn)
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA
IF — ID EX ⋅ ⋅ ⋅
IF ID EX ⋅ ⋅ ⋅
Section 8 Pipeline Operation
Operation
The pipeline ends after four stages: IF, ID, EX, MA. There is no WB stage as there is no return of
data to the register.
Instruction Issuance
These instructions use the memory access pipeline.
Parallel Execution Capability
These are 32-bit instructions, and cannot be used in parallel execution. (See section 8.3.5, Details
of Contention Due to 32-Bit Instruction.)
Rev. 3.00 Jul 08, 2005 page 387 of 484
REJ09B0051-0300