SH-2A Datasheet, PDF (459/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(2) Address Error Exception Handling
Instruction Type
Address error exception handling
Pipeline
Address error
exception handling
Next instruction
Instruction after next
Branch destination
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX EX MA MA MA
IF ⋅ ⋅ ⋅
IF ⋅ ⋅ ⋅
IF ID
Operation
An address error is accepted in the ID stage of an instruction, and processing from that ID stage
onward is replaced by the address error exception handling sequence.
The pipeline ends after seven stages: IF, ID, EX, EX, MA, MA, MA. Address error exception
handling is not a delayed branch. The IF stage of the branch destination instruction is started from
the slot containing the last MA stage of the address error exception handling.
Address error generation sources comprise those related to an instruction fetch, and those related
to a data read or write. See the hardware manual for details of generation sources.
Address Error Exception Handling Acceptance
Address error exception handling is not accepted in a delay slot.
If a multi-cycle instruction is currently being executed, address error exception handling is not
accepted until after execution of that instruction is completed. However, a DIVU or DIVS
instruction can be canceled during execution, allowing address error exception handling to be
accepted.
Rev. 3.00 Jul 08, 2005 page 445 of 484
REJ09B0051-0300