SH-2A Datasheet, PDF (392/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
8.9.1 Data Transfer Instructions
(1) Register-Register Transfer Instructions (MOV Rm,Rn)
Instruction Type
MOV Rm,Rn
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ Slots
IF ID EX
IF ID EX ⋅ ⋅ ⋅
IF ID EX ⋅ ⋅ ⋅
Operation
The pipeline ends after three stages: IF, ID, EX. In the EX stage, data transfer is performed via
the ALU.
Instruction Issuance
This instruction does not cause resource contention.
Parallel Execution Capability
This is a zero-latency instruction. Parallel execution is possible even when this instruction is
executed as a preceding instruction and the succeeding instruction uses Rn.
Rev. 3.00 Jul 08, 2005 page 378 of 484
REJ09B0051-0300