SH-2A Datasheet, PDF (341/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 7 Register Banks
(2) Bank Number Register (IBNR) (16 bit, Initial value: H'0000)
Bit 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BE1 BE0 BOVE — — — — — — — — — BN3 BN2 BN1 BN0
The setting of the bank number register (IBNR) is used to allow or prohibit use of register banks
and to allow or prohibit register bank overflow exceptions. In addition, bits BN3 to BN0 indicate
the number of the next bank to be saved to. They are initialized to H'0000 by a power-on reset.
Bits 15 and 14: BE1, BE0
These bits specify whether register bank use is prohibited or allowed.
Bits 15, 14
BE1, BE0
00
01
10
11
Description
Use of the bank is prohibited for all interrupts. The setting of IBCR is ignored.
(Initial value)
Use of the bank is prohibited for all interrupts except NMI and UBC. The setting
of IBCR is ignored.
Reserved. (Do not attempt to set this bit.)
Use of the bank is as specified by IBCR.
Bit 13: BOVE
This bit specify whether register bank overflow exceptions are prohibited or allowed.
Bit 13
BOVE
0
1
Description
Generation of register bank overflow exceptions is prohibited.
(Initial value)
Generation of register bank overflow exceptions is allowed.
Bits 12 to 4: Reserved Bits
These bits are always read as 0 and only a value of 0 should be written to them.
Bits 3 to 0: BN3 to BN0
These bits indicate the number of the next bank to be saved to. When an interrupt that uses a
register bank is received, it is saved to the bank specified by BN3 to BN0 and BN is incremented
by 1. Execution of a register bank retrieve instruction causes BN to be decremented by 1, after
which the data is retrieved from the register bank. These bits are read-only and cannot be
modified.
Rev. 3.00 Jul 08, 2005 page 327 of 484
REJ09B0051-0300