SH-2A Datasheet, PDF (145/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.3.22
MOVI20S
MOVe Immediate 20bits data
and 8bits Shift left
20-Bit Immediate Data Transfer and 8-Bit Left-Shift
Data Transfer Instruction
SH-2A/SH2A-FPU (New)
Format
MOVI20S #imm20, Rn
Abstract
imm<<8 → sign
extension → Rn
Code
0000nnnniiii0001iiiiiiiiiiiiiiii
Cycle T Bit
1
―
Description
Shifts immediate data 8 bits to the left and performs sign extension to longword, then stores the
resulting data in general register Rn. Using an OR or ADD instruction as the next instruction
enables a 28-bit absolute address to be generated. See section Appendix B, Programming
Guidelines, for details.
MOVI20S
19
0
imm
20 bits
31 27
Rn
20 bits
8
0
00000000
Sign extension
Note
For the Renesas Technology Super H RISC engine assembler, declarations should use immediate
data that has been shifted 8 bits to the left.
Rev. 3.00 Jul 08, 2005 page 131 of 484
REJ09B0051-0300