SH-2A Datasheet, PDF (439/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(4) LDC.L and LDS.L Instructions
Instruction Types
LDC.L
LDC.L
LDS.L
@Rm+,GBR
@Rm+,VBR
@Rm+,PR
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA WB
IF ID EX ⋅ ⋅ ⋅
IF ID EX ⋅ ⋅ ⋅
Operation
The pipeline ends after five stages: IF, ID, EX, MA, WB.
Instruction Issuance
These instructions use the memory access pipeline.
Parallel Execution Capability
No particular comments
Rev. 3.00 Jul 08, 2005 page 425 of 484
REJ09B0051-0300