SH-2A Datasheet, PDF (368/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
When a register (FPUL) that stores the result of a floating-point arithmetic operation instruction is
read (used as a source register) by a following STS instruction, and the value is output to the CPU,
latency is shortened by 2 cycles (figure 8.38).
Floating-point arithmetic operation
instruction (single-precision)
(FTRC FR0,FPUL)
Next floating-point instruction
(single-precision)
(STS FPUL,R3)
IF DF E1 E2 SF
IF DF EX NA
Figure 8.38 Example of Transferring Result to CPU Immediately Following FPU Operation
The time required for the result of an FCMP instruction to be reflected in the T bit is 2 cycles in
the case of single-precision, and 3 cycles in the case of double-precision. As a result, if that
instruction (the following instruction) references the T bit, execution is delayed by the above slot
interval (figure 8.39).
Instruction 1 (single-precision)
(FCMP FR0,FR1)
Instruction 2 (instruction that
references T bit)
(BF)
IF DF E1 E2
IF — ID EX
Figure 8.39 Example of Referencing T Bit Immediately After FCMP Instruction
When the FPSCR value is changed using an LDS or LDS.L instruction, execution of the next
instruction by a 3-slot interval (figure 8.40).
Instruction 1
(LDS R2,FPSCR)
Instruction 2
(FADD FR4,FR5)
IF DF EX NA SF
IF — — — DF E1 E2 SF
Figure 8.40 Example of Performing FPU Operation Immediately After FPSCR Load
Rev. 3.00 Jul 08, 2005 page 354 of 484
REJ09B0051-0300