SH-2A Datasheet, PDF (269/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.4.56
SHLRn
n-Bit Right
Logical Shift
n bits SHift Logical Right
Section 6 Instruction Descriptions
Shift Instruction
Format
SHLR2 Rn
SHLR8 Rn
SHLR16 Rn
Abstract
Rn>>2 → Rn
Rn>>8 → Rn
Rn>>16 → Rn
Code
0100nnnn00001001
0100nnnn00011001
0100nnnn00101001
Cycle
1
1
1
T Bit
—
—
—
Description
Logically shifts the contents of general register Rn to the right by 2, 8, or 16 bits, and stores the
result in Rn. Bits that are shifted out of the operand are not stored (figure 6.12).
MSB
LSB
SHLR2
0
MSB
LSB
SHLR8
0
MSB
LSB
SHLR16
0
Figure 6.12 Shift Logical Right n Bits
Rev. 3.00 Jul 08, 2005 page 255 of 484
REJ09B0051-0300