SH-2A Datasheet, PDF (498/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Appendix B Programming Guidelines (Using MOVI20 and MOVI20S)
Notes: To specify addresses in the range H'07FF FF80–H'07FF FFFF:
MOVI20S #imm20, R0
OR #imm, R0
Unconditional branch instruction*
Alternately, use a 32-bit address read as follows:
MOV.L @(disp, PC), Rn
Unconditional branch instruction*
* Unconditional branch instruction: BRAF Rm, BSRF Rm, JMP @Rm, JSR @Rm,
JSR/N @Rm
Rev. 3.00 Jul 08, 2005 page 484 of 484
REJ09B0051-0300