SH-2A Datasheet, PDF (246/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.4.37
MULS.W
Signed
Multiplication
MULtiply as Signed Word
Arithmetic Instruction
Format
MULS.W Rm,Rn
MULS Rm,Rn
Abstract
Signed operation, Rn × Rm → MACL
Code
0010nnnnmmmm1111
Cycle
1
T Bit
—
Description
Performs 16-bit multiplication of the contents of general registers Rn and Rm, and stores the 32-
bit result in the MACL register. The operation is signed and the MACH register data does not
change.
Operation
MULS(long m,long n) /* MULS Rm,Rn */
{
MACL=((long)(short)R[n]*(long)(short)R[m]);
PC+=2;
}
Example:
MULS R0,R1 ; Before execution:
; After execution:
STS MACL,R0 ; Operation result
R0 = H'FFFFFFFE, R1 = H'00005555
MACL = H'FFFF5556
Rev. 3.00 Jul 08, 2005 page 232 of 484
REJ09B0051-0300