SH-2A Datasheet, PDF (58/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 4 Instruction Features
Instruction Formats
nmd12 format
32
16
xxxx nnnn mmmm xxxx
15
0
xxxx dddd dddd dddd
d format
15
xxxx xxxx
0
dddd dddd
d12 format
15
xxxx dddd
nd8 format
15
xxxx nnnn
i format
15
xxxx xxxx
dddd
dddd
iiii
0
dddd
0
dddd
0
iiii
ni format
15
0
xxxx nnnn i i i i i i i i
Source
Operand
mmmm:
Register direct
mmmmdddd:
Register indirect
with
displacement
dddddddd: GBR
indirect with
displacement
R0 (register
direct)
dddddddd: PC-
relative with
displacement
dddddddd: TBR
duplicate
indirect with
displacement
dddddddd: PC-
relative
dddddddddddd:
PC relative
Destination
Operand
nnnndddd:
Register indirect
with displacement
nnnn: Register
direct
R0 (register direct)
dddddddd: GBR
indirect with
displacement
R0 (register direct)
—
—
—
Example
MOV.L
Rm,@(disp12, Rn)
MOV.L
@(disp12,Rm), Rn
MOV.L
@(disp,GBR),R0
MOV.L
R0,@(disp,GBR)
MOVA
@(disp,PC),R0
JSR/N
@@(disp8,TBR)
BF label
BRA label
(label = disp + PC)
dddddddd: PC
relative with
displacement
iiiiiiii:
Immediate
iiiiiiii:
Immediate
iiiiiiii:
Immediate
iiiiiiii:
Immediate
nnnn: Direct
register
MOV.L
@(disp,PC),Rn
Indirect indexed
GBR
AND.B
#imm,@(R0,GBR)
R0 (Direct register) AND #imm,R0
—
TRAPA #imm
nnnn: Direct
register
ADD #imm,Rn
Rev. 3.00 Jul 08, 2005 page 44 of 484
REJ09B0051-0300