SH-2A Datasheet, PDF (417/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(8) DIVS Instruction
Instruction Type
DIVS R0,Rn
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX ⋅ ⋅ ⋅ EX EX
IF — — — ID EX ⋅ ⋅ ⋅
IF — — — ID EX ⋅ ⋅ ⋅
Operation
The pipeline ends after 38 stages: IF, ID, EX, EX, EX, EX, EX, EX, EX, EX, EX, EX, EX, EX,
EX, EX, EX, EX, EX, EX, EX, EX, EX, EX, EX, EX, EX, EX, EX, EX, EX, EX, EX, EX, EX,
EX, EX, EX. Data operations are completed using the ALU in the EX stages.
Instruction Issuance
This instruction do not cause resource contention.
Parallel Execution Capability
This is a multi-cycle instruction, and cannot be executed in parallel with a subsequent instruction.
Rev. 3.00 Jul 08, 2005 page 403 of 484
REJ09B0051-0300