SH-2A Datasheet, PDF (52/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 4 Instruction Features
Addressing Instruction
Mode
Format
Indirect
register
addressing
with
displace-
ment
@(disp:4,
Rn)
Effective Addresses Calculation
Formula
The effective address is Rn plus a 4-bit displacement
(disp). The value of disp is zero-extended, and
remains the same for a byte operation, is doubled for
a word operation, or is quadrupled for a longword
operation.
Rn
Byte: Rn +
disp
Word: Rn +
disp × 2
Longword:
Rn + disp × 4
disp
(zero-extended)
+
Rn
+ disp 1/2/4
Indirect
indexed
register
addressing
@(disp:12,
Rn)
@(R0, Rn)
1/2/4
Effective address is register Rn contents with 12-bit
displacement disp added. disp is zero-extended.
Rn
+
Rn + disp
disp
(zero-extended)
The effective address is the Rn value plus R0.
Rn
+
Rn + R0
Byte: Rn +
disp
Word: Rn +
disp
Longword:
Rn + disp
Rn + R0
Indirect
GBR
addressing
with
displace-
ment
@(disp:8,
GBR)
R0
The effective address is the GBR value plus an 8-bit
displacement (disp). The value of disp is zero-
extended, and remains the same for a byte
operation, is doubled for a word operation, or is
quadrupled for a longword operation.
GBR
disp
(zero-extended)
+
GBR
+ disp 1/2/4
Byte: GBR +
disp
Word: GBR +
disp × 2
Longword:
GBR + disp ×
4
1/2/4
Rev. 3.00 Jul 08, 2005 page 38 of 484
REJ09B0051-0300