SH-2A Datasheet, PDF (382/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
Type
Category
Number Execution
of Stages States
Latency
Arithmetic Inter-
3
operation register
instructions arithmetic
operation
instructions
(excluding
multiply
instruc-
tions)
1
1
Inter-
register
arithmetic
operations
instructions
(excluding
multiply
instructions
and DIVU
or DIVS
instruc-
tions)
CLIP
3
instructions
1
1
Contention
—
—
Instructions
ADD
Rm,Rn
ADD
#imm,Rn
ADDC Rm,Rn
ADDV Rm,Rn
CMP/EQ #imm,R0
CMP/EQ Rm,Rn
CMP/HS Rm,Rn
CMP/GE Rm,Rn
CMP/HI Rm,Rn
CMP/GT Rm,Rn
CMP/PZ Rn
CMP/PL Rn
CMP/STR Rm,Rn
DIV1
Rm,Rn
DIV0S Rm,Rn
DIV0U
DT
Rn
EXTS.B Rm,Rn
EXTS.W Rm,Rn
EXTU.B Rm,Rn
EXTU.W Rm,Rn
NEG
Rm,Rn
NEGC Rm,Rn
SUB
Rm,Rn
SUBC Rm,Rn
SUBV Rm,Rn
CLIPU.B Rn
CLIPU.W Rn
CLIPS.B Rn
CLIPS.W Rn
Rev. 3.00 Jul 08, 2005 page 368 of 484
REJ09B0051-0300