SH-2A Datasheet, PDF (129/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.3.15 FMOV
Floating-point MOVe
Floating-Point Transfer
Section 6 Instruction Descriptions
Floating-Point Instruction
SH-2A/SH2A-FPU (New)
No. SZ
10
21
30
41
Format
Abstract
Code
Cycle T Bit
FMOV.S FRm, @(disp12,Rn) FRm → (disp×4+Rn) 0011nnnnmmmm00010011dddddddddddd 1
―
FMOV.D DRm, @(disp12,Rn) DRm → (disp×8+Rn) 0011nnnnmmm000010011dddddddddddd 2
―
FMOV.S @(disp12,Rm), FRn (disp×4+Rm) → FRn 0011nnnnmmmm00010111dddddddddddd 1
―
FMOV.D @(disp12,Rm), DRn (disp×8+Rm) → DRn 0011nnn0mmmm00010111dddddddddddd 2
―
Description
1. Transfers FRm contents to memory at the address indicated by (disp + Rn).
2. Transfers DRm contents to memory at the address indicated by (disp + Rn).
3. Transfers memory contents at the address indicated by (disp + Rn) to FRn.
4. Transfers memory contents at the address indicated by (disp + Rn) to DRn.
Note
For the Renesas Technology Super H RISC engine assembler, declarations should use scaled
values (×4, ×8) as displacement values.
Operation
void FMOV_INDEX_DISP12_STORE(int
{
long disp;
m,n)
/*FMOV.S FRm, @(disp12,Rn) */
disp = (0x00000FFF & (long)d);
Write_Int ( R[n]+(disp<<2), FR[m]);
PC +=4;
}
void FMOV_INDEX_DISP12_STORE_DR(int m,n)
/*FMOV.D DRm, @(disp12,Rn) */
{
long disp;
disp = (0x00000FFF & (long)d);
Rev. 3.00 Jul 08, 2005 page 115 of 484
REJ09B0051-0300