SH-2A Datasheet, PDF (271/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.4.57 SLEEP
SLEEP
Transition to Power-Down Mode
Format
SLEEP
Abstract
Sleep
Section 6 Instruction Descriptions
System Control Instruction
Code
0000000000011011
Cycle
5
T Bit
—
Description
Sets the CPU into power-down mode. In power-down mode, instruction execution stops, but the
CPU internal status is maintained, and the CPU waits for an interrupt request. If an interrupt is
requested, the CPU exits the power-down mode and begins exception processing.
Note
The number of cycles given is for the transition to sleep mode.
Operation
SLEEP() /* SLEEP */
{
wait_for_exception;
}
Example:
SLEEP ; Enters power-down mode
Rev. 3.00 Jul 08, 2005 page 257 of 484
REJ09B0051-0300