SH-2A Datasheet, PDF(208/501 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

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SH-2A Datasheet, PDF (208/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

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Section 6 Instruction Descriptions

6.4.20

DMULU.L

Double-length MULtiply

as Unsigned

Unsigned Double-Length

Multiplication

Arithmetic Instruction

Format

DMULU.L Rm, Rn

Abstract

Without sign, Rn Ã Rm â MACH,

MACL

Code

Cycle T Bit

0011nnnnmmmm0101 2

â

Description

Performs 32-bit multiplication of the contents of general registers Rn and Rm, and stores the 64-

bit results in the MACL and MACH register. The operation is an unsigned arithmetic operation.

Operation

DMULU(long m,long n) /* DMULU.L Rm,Rn */

{

unsigned long RnL,RnH,RmL,RmH,Res0,Res1,Res2;

unsigned long temp0,temp1,temp2,temp3;

RnL=R[n]&0x0000FFFF;

RnH=(R[n]>>16)&0x0000FFFF;

RmL=R[m]&0x0000FFFF;

RmH=(R[m]>>16)&0x0000FFFF;

temp0=RmL*RnL;

temp1=RmH*RnL;

temp2=RmL*RnH;

temp3=RmH*RnH;

Res2=0

Res1=temp1+temp2;

if (Res1<temp1) Res2+=0x00010000;

temp1=(Res1<<16)&0xFFFF0000;

Rev. 3.00 Jul 08, 2005 page 194 of 484

REJ09B0051-0300

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