SH-2A Datasheet, PDF (325/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.5.15
FSCHG
SZ Bit
Inversion
Sz-bit CHanGe
Section 6 Instruction Descriptions
Floating-Point Instruction
PR Format
0
FSCHG
1
—
Abstract
FPSCR.SZ=~FPSCR.SZ
—
Code
Cycle
1111001111111101 1
—
—
T Bit
—
—
Description
When FPSCR.PR = 0, this instruction inverts the SZ bit in floating-point register FPSCR.
Changing the SZ bit in FPSCR switches FMOV instruction data transfer between one single-
precision data unit and a data pair. When FPSCR.SZ = 0, the FMOV instruction transfers one
single-precision data unit. When FPSCR.SZ = 1, the FMOV instruction transfers two single-
precision data units as a pair.
If FPSCR.PR = 1, the instruction is handled as an illegal instruction.
Operation
void FSCHG() /* FSCHG */
{
if(FPSCR_PR == 0){
FPSCR ^= 0x00100000; /* bit 20 */
PC += 2;
}
else undefined_operation();
}
Possible Exceptions:
None
Rev. 3.00 Jul 08, 2005 page 311 of 484
REJ09B0051-0300