SH-2A Datasheet, PDF (301/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.5.5 FCNVSD
Single-Precision
to Double-Precision
Conversion
Section 6 Instruction Descriptions
Floating-point CoNVert
Single to Double precision Floating-Point Instruction
PR Format
Abstract
0—
—
1 FCNVSD FPUL, DRn (double) FPUL → DRn
Code
Cycle
—
—
1111nnn010101101 2
T Bit
—
—
Description
When FPSCR.PR = 1, this instruction converts the single-precision floating-point number in
FPUL to a double-precision floating-point number, and stores the result in DRn.
If FPSCR.PR = 0, the instruction is handled as an illegal instruction.
Operation
void FCNVSD(int n, float *FPUL){
pc += 2;
clear_cause();
case((FPSCR_PR){
0: undefined_operation(); /* reserved */
1: fcnvsd (n, *FPUL); break; /* FCNVSD */
}
}
void fcnvsd(int n, float *FPUL)
{
case(fpul_type(FPUL)){
PZERO :
NZERO :
PINF :
NINF :
DR[n>>1] = *FPUL;
break;
qNaN :
qnan(n);
break;
sNaN :
invalid(n);
break;
}
Rev. 3.00 Jul 08, 2005 page 287 of 484
REJ09B0051-0300