SH-2A Datasheet, PDF (397/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(5) Memory Load Instructions (12-Bit Displacement)
Instruction Types
MOV.B @(disp12,Rm),Rn
MOV.W @(disp12,Rm),Rn
MOV.L @(disp12,Rm),Rn
MOVU.B @(disp12,Rm),Rn
MOVU.W @(disp12,Rm),Rn
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA WB
IF ID EX ⋅ ⋅ ⋅
IF ID EX ⋅ ⋅ ⋅
Operation
The pipeline has five stages: IF, ID, EX, MA, WB. Contention may occur if an instruction that
uses the destination register of this instruction is located within the 2 instructions following this
instruction. (See section 8.5, Effect of Memory Load Instruction on Pipeline.)
Instruction Issuance
These instructions use the memory access pipeline.
Parallel Execution Capability
These are 32-bit instructions, and cannot be executed in parallel with a subsequent instruction.
(See section 8.3.5, Details of Contention Due to 32-Bit Instruction.)
Rev. 3.00 Jul 08, 2005 page 383 of 484
REJ09B0051-0300