SH-2A Datasheet, PDF (306/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
FDIV Special Cases
FRm,DRm
FRn,DRn
NORM
+0
–0
+INF
–INF
NORM
DIV
0
INF
+0
DZ
Invalid
+INF
–INF
–0
–INF
+INF
+INF
0
+0
–0
Invalid
–INF
–0
+0
qNaN
sNaN
Note: The value of a denormalized number is treated as 0.
qNaN sNaN
qNaN
Invalid
Possible Exceptions:
• Invalid operation
• Divide by zero
• Overflow
• Underflow
• Inexact
Rev. 3.00 Jul 08, 2005 page 292 of 484
REJ09B0051-0300