SH-2A Datasheet, PDF (47/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 4 Instruction Features
Section 4 Instruction Features
4.1 RISC-Type Instruction Set
All instructions are RISC type. Their features are detailed in this section.
(1) 16-Bit Fixed-Length Instructions
Basic instructions have a fixed length of 16 bits, increasing program code efficiency.
(2) Addition of 32-Bit Fixed-Length Instructions
The SH-2A/SH2A-FPU features the addition of 32-bit fixed-length instructions, improving
performance and ease of use.
(3) One Instruction/Cycle
Basic instructions can be executed in one cycle using the pipeline system.
(4) Data Length
Longword is the standard data length for all operations. Memory can be accessed in bytes, words,
or longwords. Byte or word data accessed from memory is sign-extended and calculated with
longword data. Immediate data is sign-extended for arithmetic operations or zero-extended for
logic operations. It also is calculated with longword data.
Table 4.1 Sign Extension of Word Data
SH-2A/SH2A-FPU CPU
Description
Example for Other CPU
MOV.W
ADD
.........
.DATA.W
@(disp,PC),R1
R1,R0
H'1234
Data is sign-extended to 32
bits, and R1 becomes
H'00001234. It is next
operated upon by an ADD
instruction.
ADD.W #H'1234,R0
Note: The address of the immediate data is accessed by @(disp, PC).
(5) Load-Store Architecture
Basic operations are executed between registers. For operations that involve memory access, data
is loaded to the registers and executed (load-store architecture). Instructions such as AND that
manipulate bits, however, are executed directly in memory.
Rev. 3.00 Jul 08, 2005 page 33 of 484
REJ09B0051-0300