SH-2A Datasheet, PDF (72/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 5 Instruction Set
5.1.2 Arithmetic Operation Instructions
Table 5.4 Arithmetic Operation Instructions
Instruction
ADD
Rm, Rn
ADD
#imm, Rn
ADDC Rm, Rn
ADDV Rm, Rn
CMP/EQ #imm, R0
CMP/EQ Rm, Rn
CMP/HS Rm, Rn
CMP/GE Rm, Rn
CMP/HI Rm, Rn
CMP/GT Rm, Rn
CMP/PL Rn
CMP/PZ Rn
CMP/STR Rm, Rn
CLIPS.B Rn
Code
Operation
0011nnnnmmmm1100 Rn + Rm → Rn
0111nnnniiiiiiii Rn + imm → Rn
0011nnnnmmmm1110 Rn + Rm + T → Rn, carry → T
0011nnnnmmmm1111 Rn + Rm → Rn, overflow → T
10001000iiiiiiii When R0 = imm, 1 → T
Otherwise, 0 → T
0011nnnnmmmm0000 When Rn = Rm, 1 → T
Otherwise, 0 → T
0011nnnnmmmm0010 When Rn ≥ Rm (unsigned), 1 → T
Otherwise, 0 → T
0011nnnnmmmm0011 When Rn ≥ Rm (signed), 1 → T
Otherwise, 0 → T
0011nnnnmmmm0110 When Rn > Rm (unsigned), 1 → T
Otherwise, 0 → T
0011nnnnmmmm0111 When Rn > Rm (signed), 1 → T
Otherwise, 0 → T
0100nnnn00010101 When Rn > 0, 1 → T
Otherwise, 0 → T
0100nnnn00010001 When Rn ≥ 0, 1 → T
Otherwise, 0 → T
0010nnnnmmmm1100 When any bytes are equal, 1 → T
Otherwise, 0 → T
0100nnnn10010001 When Rn > (H'0000007F),
(H'0000007F) → Rn, 1 → CS
When Rn < (H'FFFFFF80),
(H'FFFFFF80) → Rn, 1 → CS
Compatibility
Cycles
T Bit
New
SH2E
SH4
SH-2A/
SH2A-
FPU
1
―
Yes Yes
1
―
Yes Yes
1 Carry
Yes Yes
1 Overflow Yes Yes
1 Com-
Yes Yes
parison
result
1 Com-
Yes Yes
parison
result
1 Com-
Yes Yes
parison
result
1 Com-
Yes Yes
parison
result
1 Com-
Yes Yes
parison
result
1 Com-
Yes Yes
parison
result
1 Com-
Yes Yes
parison
result
1 Com-
Yes Yes
parison
result
1 Com-
Yes Yes
parison
result
1
―
Yes
Rev. 3.00 Jul 08, 2005 page 58 of 484
REJ09B0051-0300