SH-2A Datasheet, PDF (210/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.4.21 DT
Decrement and Test
Decrement and Test
Arithmetic Instruction
Format
DT Rn
Abstract
Rn – 1 → Rn; When Rn is 0, 1 → T,
when Rn is nonzero, 0 → T
Code
Cycle T Bit
0100nnnn00010000 1
Comparison
result
Description
The contents of general register Rn are decremented by 1 and the result compared to 0 (zero).
When the result is 0, the T bit is set to 1. When the result is not zero, the T bit is set to 0.
Operation
DT(long n) /* DT Rn */
{
R[n]--;
if (R[n]==0) T=1;
else T=0;
PC+=2;
}
Example:
MOV
LOOP:
ADD
DT
BF
#4,R5 ; Sets the number of loops.
R0,R1
R5
LOOP
;
; Decrements the R5 value and checks whether it has become 0.
; Branches to LOOP is T=0. (In this example, loops 4 times.)
Rev. 3.00 Jul 08, 2005 page 196 of 484
REJ09B0051-0300