SH-2A Datasheet, PDF (158/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.3.29 PREF
PREFetch data to cache
Prefetch to Data Cache
Data Transfer Instruction
SH-2A/SH2A-FPU (New)
Format
PREF @Rn
Abstract
Prefetch cache block
Code
0000nnnn10000011
Cycle
1
T Bit
―
Description
Reads a 16-byte data block starting at a 16-byte boundary into the operand cache.
Address related errors are not generated for this instruction. In the event of an error, this
instruction is handled as an NOP (no operation) instruction.
Note
On products with no cache, this instruction is handled as a NOP instruction.
Operation
PREF (long n)
{
PC+=2;
}
/* PREF @Rn */
Examples:
SOFT_PF:
MOV.L SOFT_PF,R1
PREF @R1
.align 16
.data.w H'1234
.data.w H'5678
.data.w H'9ABC
.data.w H'DEF0
; R1 address is SOFT_PF
; Load SOFT_PF data into internal data cache
Rev. 3.00 Jul 08, 2005 page 144 of 484
REJ09B0051-0300